Memory device
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United States of America Patent
Stats
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Jan 27, 2015
Grant Date -
Jun 13, 2013
app pub date -
Dec 5, 2012
filing date -
Dec 9, 2011
priority date (Note) -
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status (Latency Note)
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Abstract
A memory device including first to fourth memory cell arrays and a driver circuit including a pair of bit line driver circuits and a pair of word line driver circuits is provided. The first to fourth memory cell arrays are overlap with the driver circuit. Each of the pair of bit line driver circuits and a plurality of bit lines are connected through connection points on an edge along the boundary between the first and second memory cell arrays or on an edge along the boundary between the third and fourth memory cell arrays. Each of the pair of word line driver circuits and a plurality of word lines are connected through second connection points on an edge along the boundary between the first and fourth memory cell arrays or on an edge along the boundary between the second and third memory cell arrays.
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