Systems and methods of sectioned bit line memory arrays
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United States of America Patent
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Nov 26, 2013
Grant Date -
Jun 13, 2013
app pub date -
Dec 9, 2011
filing date -
Dec 9, 2011
priority date (Note) -
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Abstract
A sectioned bit line of an SRAM memory device, an SRAM memory device having a sectioned bit line, and associated systems and methods are described. In one illustrative implementation, the sectioned bit line may comprise a local bit line, a memory cell connected to the local bit line, and a pass gate coupled to the local bit line, wherein the pass gate is configured to be coupled to a global bit line. In other implementations, an SRAM memory device may be configured involving sectioned bit lines and a global bit line wherein the pass gates are configured to connect and isolate the sectioned bit line and the global bit line.
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