SRAM cell having an N-well bias
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United States of America Patent
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May 13, 2014
Grant Date -
Jun 13, 2013
app pub date -
Feb 4, 2013
filing date -
Nov 16, 2010
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Abstract
A method for writing a low data bit value, writing a high data bit value, and reading a data bit value of an addressed SRAM cell. The method may include adjusting a bias level of the n-wells that contain the bit driver, bit-bar driver, bit passgate, and optional bit-bar passgate.
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