Memory circuits, systems, and operating methods thereof
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United States of America Patent
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Jun 10, 2014
Grant Date -
Jun 13, 2013
app pub date -
Feb 5, 2013
filing date -
Feb 10, 2009
priority date (Note) -
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Abstract
A memory circuit including at least one memory cell connected to a bit line. The memory circuit further includes a means for providing a bit line reference voltage VBLref to the bit line. A VBLref/VDD ratio of the bit line reference voltage VBLref to a power voltage VDD is adjustable corresponding to a change of the power voltage VDD, and the VBLref/VDD ratio ranges from about 0.4 to about 0.53.
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