Importance

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Abstract

The disclosed invention gives an estimation of the placement location of the units comprising a NoC within the floorplan of a chip. From that, and with knowledge of the number of wires of links within the NoC topology, an estimation of the wire density at each point is calculated. Furthermore, an estimate is made of the locations of the critical timing paths within the chip. The timing path calculation is also used to generate IO constraints for the synthesis of modules comprising different parts of the NoC. Further still, a scenario of traffic through the NoC is combined with the wire map and information about the width of links within the topology to generate an estimation of power consumption.

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First Claim