RESISTIVE MEMORY HAVING RECTIFYING CHARACTERISTICS OR AN OHMIC CONTACT LAYER

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United States of America Patent

APP PUB NO 20130214235A1
SERIAL NO

13881584

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Abstract

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Disclosed is a resistive memory simultaneously having rectifying characteristics and resistive characteristics according to a bias direction, wherein a resistive diode is interposed between electrodes at the top and bottom thereof. The resistive diode has a form in which a p-type resistive semiconductor layer is bonded to an n-type resistive semiconductor layer. When a high reverse bias is applied to the resistive diode, the resistive diode forms a conductive filament. When a forward bias is applied thereafter, a reset that destroys a portion of the formed conductive filament occurs, and as a result, a high resistance state is formed. Additionally, when a reverse bias is applied again, a set operation regenerating a conductive filament occurs. Thus, a low resistance state is achieved. Moreover, in order to achieve a resistive semiconductor layer and ohmic contact, and suppress the formation of a Schottky barrier, an ohmic contact layer is formed on the resistive diode. The present invention enables each memory cell to read information without misreading said information, even at a low readout voltage, and reduces the driving power required for a memory structure, such that a high-capacity and high-density memory is produced, and complexity and high costs of manufacturing processes may be avoided.

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Patent Owner(s)

Patent OwnerAddress
INDUSTRY-UNIVERSITY COOPERATION FOUNDATION HANYANG UNIVERSITYC/O HANYANG UNIVERSITY 222 WANGSIMNI-RO SEONEDONG-GU SEOUL 04763

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Bae, Yoon Cheol Gyeongsangnam-do, KR 2 11
Hong, Jin Pyo Seoul, KR 23 54
Kwak, June Sik Gyeonggi-do, KR 6 22
Lee, An Rahm Gyeongsangnam-do, KR 1 8

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