METHOD FOR MAKING GATE-OXIDE WITH STEP-GRADED THICKNESS IN TRENCHED DMOS DEVICE FOR REDUCED GATE-TO-DRAIN CAPACITANCE

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United States of America Patent

SERIAL NO

13406814

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Abstract

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A method for making gate-oxide with step-graded thickness (S-G GOX) in a trenched DMOS device is proposed. First, a substrate is provided and a silicon oxide-silicon nitride-silicon oxide (ONO) protective composite layer is formed atop. Second, an upper interim trench (UIT), an upper trench protection wall (UTPW) and a lower interim trench (LIT) are created into the substrate. Third, the substrate material surrounding the LIT is shaped and oxidized into a desired thick-oxide-layer of thickness T1 and depth D1. Fourth, previously formed UTPW is stripped off from the device in progress, then a thin-gate-oxide of thickness T2 where T21 is formed on the vertical surface of the UIT. Fifth, the UIT and LIT are filled with polysilicon then etched back into a polysilicon layer till its top surface defines a desired thin-gate-oxide depth D2.

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Patent Owner(s)

Patent OwnerAddress
ALPHA AND OMEGA SEMICONDUCTOR INCORPORATED475 OAKMEAD PKWY SUNNYVALE CA 94085

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Bhalla, Anup Santa Clara, US 323 5714
Ding, Yongping San Jose, US 26 196
Lui, Sik Sunnyvale, US 84 1692

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