Arrays of vertically stacked tiers of non-volatile cross point memory cells and methods of reading a data value stored by an array of vertically stacked tiers of non-volatile cross point memory cells
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United States of America Patent
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Jun 3, 2014
Grant Date -
Sep 12, 2013
app pub date -
Mar 26, 2013
filing date -
Apr 22, 2010
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Abstract
An array of vertically stacked tiers of non-volatile cross point memory cells includes a plurality of horizontally oriented word lines within individual tiers of memory cells. A plurality of horizontally oriented global bit lines having local vertical bit line extensions extend through multiple of the tiers. Individual of the memory cells comprise multi-resistive state material received between one of the horizontally oriented word lines and one of the local vertical bit line extensions where such cross, with such ones comprising opposing conductive electrodes of individual memory cells where such cross. A plurality of bit line select circuits individually electrically and physically connects to individual of the local vertical bit line extensions and are configured to supply a voltage potential to an individual of the global horizontal bit lines. Other embodiments and aspects are disclosed.
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