METHOD FOR IMPLEMENTING ISOLATION GATES DURING LOW-POWER MODES
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United States of America Patent
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Issued Date -
Sep 12, 2013
app pub date -
Mar 8, 2013
filing date -
Mar 8, 2012
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Abstract
A power-saving block may be isolated from a remainder of a digital circuit. To save power, the power-saving block may be powered down when not in use. To prevent the power-down process from creating metastable states in the remainder of the digital circuit, appropriate isolation gates may separate outputs of the power-saving block from the remainder of the digital circuit. Signals may be sent to the power-saving block to ensure that the output signals from the power-saving block are always the same value during the power-down process. The isolation gates may be chosen based on the value expected on the output signals during the power-down process. Assertions may be used to confirm that the correct isolation gates were selected.
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