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Abstract

An ATM (asynchronous transfer mode) cell transfer apparatus includes an input interface, a switch block, and an OAM cell processing hardware block having a memory unit. The input interface receives an SDH/SONET signal on each of a plurality of first transfer paths to output an input OAM cell corresponding to the SDH/SONET signal to one of a plurality of input ports of the switch block corresponding to the first transfer path for the SDH/SONET signal to be transferred. The switch block receives the input OAM (operation and maintenance) cell from the corresponding input port as an OAM input port to output to the OAM cell processing hardware block together with a port number of the OAM input port, and receives at least one output OAM cell from the OAM cell processing hardware block to output to at least one of the plurality of output ports based on the received output OAM cell. The OAM cell processing hardware block reads out the at least one output OAM cell corresponding to the input OAM cell from the memory unit based on the input OAM cell and the port number supplied from the switch block, and outputs the at least one output OAM cell to the switch block.

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First Claim