Analog Rule Check Waiver

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United States of America Patent

APP PUB NO 20130263074A1
SERIAL NO

13901552

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ATTORNEY / AGENT: (SPONSORED)

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Abstract

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When a designer designates one or more errors identified in layout design data as false errors, waiver geometric elements corresponding to the designated false errors are created and added to the design. The waiver geometric element may be associated with a verification rule that generated its corresponding false error. When the design is subsequently analyzed using those verification rules in another verification rule check process, the waiver geometric elements are examined, and used to mask those errors associated with a waiver geometric element that would otherwise be displayed to the designer.

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Patent Owner(s)

Patent OwnerAddress
MENTOR GRAPHICS CORPORATIONWILSONVILLE OR 97070-7777

International Classification(s)

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Ferguson, John G Tualatin, US 22 351

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