CIRCUITS AND METHODS TO GUARANTEE LOCK IN DELAY LOCKED LOOPS AND AVOID HARMONIC LOCKING

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United States of America Patent

APP PUB NO 20130271193A1
SERIAL NO

13532241

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ATTORNEY / AGENT: (SPONSORED)

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Abstract

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A delay locked loop (DLL) includes a phase detector (PD), a lock assistor (LA), a control voltage generator, and a voltage controlled delay line (VCDL). The PD determines a phase difference between of a reference clock and a delayed version of the reference clock and produces a pair of phase detector output signals in dependence on the determined phase difference. The LA receives the pair of phase detector output signals and produces a pair of lock assist output signals by selectively swapping the phase detector output signals. The control voltage generator receives the pair of lock assist output signals and produces a control voltage signal in dependence on thereon. The VCDL receives the control voltage signal and the reference clock (or a buffered version thereof) and outputs the delayed version of the reference clock, with a delay through the VCDL being dependent on the received control voltage signal.

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Patent Owner(s)

Patent OwnerAddress
INTERSIL AMERICAS LLC1001 MURPHY RANCH ROAD MILPITAS CA 95035

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Keith, Colby Santa Clara, US 2 61

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