Method and Apparatus for Improving Efficiency of Programmable Logic Circuit Using Cascade Configuration
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United States of America Patent
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Issued Date -
Oct 24, 2013
app pub date -
Apr 18, 2013
filing date -
Apr 18, 2012
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Abstract
An integrated circuit (“IC”) device capable of programmably performing user selected functions is disclosed. The IC device, in one embodiment, includes multiple input output (“I/O”) blocks, programmable interconnection blocks (“PIBs”), and programmable logic blocks (“PLBs”). While the I/O blocks can be selectively coupled to one of I/O pads, the PIB blocks can be selectively coupled to at least a portion of the I/O blocks. Each of the PLBs, in one aspect, is configured to have at least two programmable look-up tables (“LUTs”). The programmable LUTs are connected in a cascade configuration via a dedicated programmable wire (“DPW”).
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