MANAGING BUFFER MEMORY
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United States of America Patent
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Issued Date -
Nov 7, 2013
app pub date -
May 1, 2013
filing date -
May 2, 2012
priority date (Note) -
Abandoned
status (Latency Note)
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Abstract
A computing system comprises: one or more processors; and a memory system including one or more first level memories. Each first level memory is coupled to a corresponding one of the processors. Each processor is configured to execute instructions in an instruction set, at least some of the instructions in the instruction set accessing chunks of memory in the memory system. Each processor includes a plurality of storage locations, with at least some of the instructions each specifying a set of storage locations including: a first storage location in a first of the processors storing a unique identifier of a first chunk, and a second storage location in the first processor storing a reusable identifier of a storage area in the corresponding first level memory storing the first chunk.
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