Multiple-port memory device comprising single-port memory device with supporting control circuitry
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United States of America Patent
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Jan 14, 2014
Grant Date -
Nov 14, 2013
app pub date -
Jul 17, 2013
filing date -
Mar 2, 2011
priority date (Note) -
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Abstract
An apparatus comprises a clock generator, first and second memory drivers and a multiple-port memory device having at least first and second ports configured to receive input signals from and supply output signals to respective ones of the first and second memory drivers, the multiple-port memory device further comprising a single-port memory device and control circuitry coupled between the first and second ports and the single port of the single-port memory device. The clock generator generates first and second clock signals having respective first and second clock rates, the clock rate of the second clock signal being an integer multiple of the clock rate of the first clock signal. The first and second memory drivers are configured to operate using the first clock signal at the first clock rate, and the single-port memory device is configured to operate using the second clock signal at the second clock rate.
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