Techniques for providing a direct injection semiconductor memory device
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United States of America Patent
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Oct 14, 2014
Grant Date -
Dec 5, 2013
app pub date -
Aug 12, 2013
filing date -
Apr 27, 2009
priority date (Note) -
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Abstract
Techniques for providing a direct injection semiconductor memory device are disclosed. In one particular exemplary embodiment, the techniques may be realized as a method for biasing a direct injection semiconductor memory device. The method may comprise applying a first voltage potential to a first N-doped region via a bit line and applying a second voltage potential to a second N-doped region via a source line. The method may also comprise applying a third voltage potential to a word line, wherein the word line is spaced apart from and capacitively coupled to a body region that is electrically floating and disposed between the first N-doped region and the second N-doped region. The method may further comprise applying a fourth voltage potential to a P-type substrate via a carrier injection line.
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