SELF-ALIGNED SI RICH NITRIDE CHARGE TRAP LAYER ISOLATION FOR CHARGE TRAP FLASH MEMORY

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United States of America Patent

SERIAL NO

14019192

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Abstract

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A method for fabricating a memory device with U-shaped trap layers over rounded active region corners is disclosed. In the present invention, an STI process is performed before the charge-trapping layer is formed. Immediately after the STI process, the sharp corners of the active regions are exposed, making them available for rounding. Rounding the corners improves the performance characteristics of the memory device. Subsequent to the rounding process, a bottom oxide layer, nitride layer, and sacrificial top oxide layer are formed. An organic bottom antireflective coating applied to the charge trapping layer is planarized. Now the organic bottom antireflective coating, sacrificial top oxide layer, and nitride layer are etched, without etching the sacrificial top oxide layer and nitride layer over the active regions. After the etching the charge trapping layer has a cross-sectional U-shape appearance. U-shaped trap layer edges allow for increased packing density and integration while maintaining isolation between trap layers.

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Patent Owner(s)

Patent OwnerAddress
SPANSION LLC915 DEGUIGNE DRIVE P O BOX 3453 MAIL STOP 250 SUNNYVALE CA 94088-3453

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
FANG, Shenqing Fremont, US 127 970
HUI, Angela Fremont, US 52 851
KANG, Inkuk San Jose, US 27 319
TING, Shao-Yu Kaohsiung City, TW 5 15
XUE, Gang Sunnyvale, US 33 211

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