PHASE LOCKED LOOP CIRCUIT WITH SELECTABLE FEEDBACK PATHS
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United States of America Patent
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app pub date -
Sep 9, 2013
filing date -
Apr 4, 2011
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Abandoned
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Abstract
In one embodiment, a phase locked loop (PLL) circuit in a device includes selectable feedback paths and a multiplexer. An internal feedback path is adapted to pass a first input clock signal to the PLL circuit during a low power operation mode of the device and an external feedback path is adapted to pass a second input clock signal to the PLL circuit during a normal operation mode of the device. The multiplexer is provided for selecting between the internal and external feedback paths.
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