PLATEABLE DIFFUSION BARRIER TECHNIQUES
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United States of America Patent
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Issued Date -
Jan 16, 2014
app pub date -
Jul 10, 2012
filing date -
Jul 10, 2012
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Abstract
Techniques are disclosed for forming a directly plateable diffusion barrier within an interconnect structure to prevent diffusion of interconnect fill metal into surrounding dielectric material and lower metal layers. The barrier can be used in back-end interconnect metallization processes and, in an embodiment, renders a seed layer unnecessary. In accordance with various example embodiments, the barrier can be implemented, for instance, as: (1) a single layer of ruthenium silicide (RuSix) or ruthenium silicide nitride (RuSixNy); (2) a bi-layer of Ru/RuSix, RuSix/Ru, Ru/RuSixNy, or RuSixNy/Ru; or (3) a tri-layer of Ru/RuSix/Ru or Ru/RuSixNy/Ru. In some embodiments, Si and/or N concentrations can be adjusted to alter the barrier's degree of diffusion protection, receptiveness to the fill metal, and/or electrical conductivity.
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