Buffer input impedance compensation in a reference clock signal buffer
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United States of America Patent
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Aug 5, 2014
Grant Date -
Jan 30, 2014
app pub date -
Jul 26, 2012
filing date -
Jul 26, 2012
priority date (Note) -
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status (Latency Note)
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Abstract
A system for managing a reference clock signal includes an XO; a signal buffer coupled to the XO and configured to drive a reference clock signal generated by the XO; and a first IC coupled to the signal buffer. The first IC includes an XO input buffer configured to receive the reference clock signal, to switch between an enabled, operational state and a disabled state, and to have a first operational impedance while in the enabled state; an impedance equivalence circuit configured to be in an enabled, operational state when the XO input buffer is in its disabled state and vice versa and to have a second operational impedance while in the enabled state that is equivalent to the first operational impedance; and a control mechanism configured to switch the XO input buffer and the impedance equivalence circuit between the enabled state and the disabled state.
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