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Abstract

A memory device having an array of memory cells and BTI-independent bias circuitry for controlling the bias voltage level of a source node of the array. The bias circuitry has an n-type transistor and a p-type transistor connected in parallel between ground and the source node. The bias circuitry also has circuitry for controlling the n-type and p-type transistors such that the memory device can be selectively configured in any of an active mode (where the source node is driven towards ground such that the array can be accessed), a low-leakage-current light sleep mode (where the source node is driven towards an intermediate, data-retention voltage level such that the array cannot be accessed but will retain data), and an even-lower-leakage-current shutdown mode (where the source node is driven towards the power supply voltage level such that the array cannot be accessed and cannot retain data).

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First Claim