MEMORY CONTROLLER RESPONSIVE TO LATENCY-SENSITIVE APPLICATIONS AND MIXED-GRANULARITY ACCESS REQUESTS

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United States of America Patent

APP PUB NO 20140052906A1
SERIAL NO

13959500

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ATTORNEY / AGENT: (SPONSORED)

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Abstract

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A multi-channel memory controller (110, 600) may be dynamically re-architected to schedule low and high-latency memory access requests differently (FIG. 12) in order to make more efficient use of memory resources and improve overall performance. Data may be duplicated or “cloned” in a clone area (612) of one or more channels of a multi-channel or module threaded memory (610), the clone area being reserved by the memory controller. Cloning information is stored in a clone mapping table 620, preferably reflecting memory channel locations, including clone locations, per memory address range. An operating system may request a selected number of channels for cloning, see (622), based on application latency requirements or sensitivity, by storing the request in the clone mapping table. Coarse granularity access requests also may be dynamically scheduled across one or more first-available channels of the multi-channel or module threaded memory (1504) in a modified controller (1500).

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Patent Owner(s)

Patent OwnerAddress
RAMBUS INC4453 N FIRST ST SUITE 100 SAN JOSE CALIFORNIA 95134 95134

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Kole, Prasanna Bangalore, IN 2 26
Malviya, Dinesh Bangalore, IN 1 13
Thyagarajan, Vidhya Bangalore, IN 6 30

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