Programmable Logic Unit and Method for Translating and Processing Instructions Using Interpretation Registers
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United States of America Patent
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Oct 27, 2013
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Sep 28, 2006
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Abstract
An architecture for microprocessors and the like in which instructions include a type identifier, which selects one of several interpretation registers. The interpretation registers hold information for interpreting the opcode of each instruction, so that a stream of compressed instructions (with type identifiers) can be translated into a stream of expanded instructions. Preferably the type identifiers also distinguish sequencer instructions from processing-element instructions, and can even distinguish among different types of sequencer instructions (as well as among different types of processing-element instructions).
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