ANTI SPACER PROCESS AND SEMICONDUCTOR STRUCTURE GENERATED BY THE ANTI SPACER PROCESS

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United States of America Patent

APP PUB NO 20140054756A1
SERIAL NO

13593503

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Abstract

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An anti spacer process, which comprises: (a) providing a resist layer including a non-uniform shape; (b) coating a target layer above the resist layer; (c) providing anti spacer trenches (spa) between the target layer and the resist layer; and (d) connecting at least part of the anti spacer trenches (spa) together to isolate a first part of the target layer and a second part of the target layer.

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Patent Owner(s)

Patent OwnerAddress
NANYA TECHNOLOGY CORPHWA-YA TECHNOLOGY PARK 669 FUHSING 3 RD KUEISHAN TAO-YUAN HSIEN

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
DEVILLIERS, ANTON Boise, US 79 849
Housley, Richard Boise, US 9 34
HYATT, MICHAEL Boise, US 19 73

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