CHIP PACKAGE STRUCTURE AND METHOD FOR MANUFACTURING SAME
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United States of America Patent
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Issued Date -
Feb 27, 2014
app pub date -
Jun 27, 2013
filing date -
Aug 27, 2012
priority date (Note) -
Abandoned
status (Latency Note)
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Abstract
A chip package structure includes a first wiring layer, a first solder mask layer, a chip and a plurality of third contact pads. The third contact pads are formed on the first wiring layer. The third contact pads and the first wiring layer are unitarily formed. The first solder mask layer is formed on the first wiring layer. The first solder mask layer defines a plurality of first openings to expose portions of the first wiring layers. The portions of the first wiring layers exposed to the first openings serve as first contact pads. The chip is mounted on the first solder mask layer and is electrically connected to the first contact pads. This disclosure further relates to a method of manufacturing the chip package structure.
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