SEMICONDUCTOR INTEGRATED CIRCUIT DESIGN APPARATUS, SEMICONDUCTOR INTEGRATED CIRCUIT DESIGN METHOD, AND STORAGE MEDIUM
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United States of America Patent
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Issued Date -
Mar 13, 2014
app pub date -
Feb 6, 2013
filing date -
Sep 7, 2012
priority date (Note) -
Abandoned
status (Latency Note)
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Abstract
According to an embodiment, in a semiconductor integrated circuit design apparatus for assigning a plurality of wires placed at one wiring layer to a plurality of photomasks, an operation-timing-critical wire is identified from among the plurality of wires placed at a same wiring layer, an adjacent wire which is placed adjacent to the critical wire is extracted, the critical wire and the adjacent wire are laid out such that an interval between the critical wire and the adjacent wire is at least a predetermined distance, and layout patterns of the critical wire and the adjacent wire is assigned to the same photomask.
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