Semiconductor Device with Increased Breakdown Voltage
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United States of America Patent
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Issued Date -
Mar 27, 2014
app pub date -
Dec 2, 2013
filing date -
Jul 28, 2006
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Abandoned
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Abstract
Optimization of the implantation structure of a metal oxide silicon field effect transistor (MOSFET) device fabricated using conventional complementary metal oxide silicon (CMOS) logic foundry technology to increase the breakdown voltage. The techniques used to optimize the implantation structure involve lightly implanting the gate region, displacing the drain region from the gate region, and implanting P-well and N-well regions adjacent to one another without an isolation region in between.
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