Wafer-level packaging of a MEMS integrated device and related manufacturing process
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United States of America Patent
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Nov 17, 2015
Grant Date -
Mar 27, 2014
app pub date -
Sep 18, 2013
filing date -
Sep 24, 2012
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Abstract
A wafer-level package for a MEMS integrated device, envisages: a first body integrating a micromechanical structure; a second body having an active region integrating an electronic circuit, coupled to the micromechanical structure; and a third body defining a covering structure for the first body. The second body defines a base portion of the package and has an inner surface coupled to which is the first body, and an outer surface provided on which are electrical contacts towards the electronic circuit; a routing layer has an inner surface set in contact with the outer surface of the second body and an outer surface that carries electrical contact elements towards the external environment. The third body defines a covering portion for covering the package and is directly coupled to the second body for closing a housing space for the first body.
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