SEMICONDUCTOR DEVICE HAVING HIERARCHICAL BIT LINE STRUCTURE
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United States of America Patent
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app pub date -
Nov 29, 2013
filing date -
Nov 19, 2010
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Abandoned
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Abstract
A method includes accessing a memory cell to allow the memory cell to output data stored therein onto a local bit line; transferring, in response to a data read mode, a signal related to the data from the local bit line to a global bit line; and restoring, in response to a refresh mode, the data into the memory cell while keeping the local bit line electrically isolated from the global bit line.
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