Wiring structure and display device
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United States of America Patent
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May 5, 2015
Grant Date -
Apr 3, 2014
app pub date -
Mar 12, 2012
filing date -
May 13, 2011
priority date (Note) -
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status (Latency Note)
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Abstract
Provided is a technique that allows oxidation of Cu wires to be effectively prevented during plasma processing when forming a passivation film for a display device that utilizes an oxide semiconductor layer. This wiring structure comprises a semiconductor layer (oxide semiconductor) for a thin film transistor, a Cu alloy film (laminated structure comprising a first layer (X) and a second layer (Z)), and a passivation film that are formed on a substrate, starting from the substrate side. The first layer (X) is made of an element that exhibits low electrical resistivity, such as pure Cu; and the second layer contains a plasma-oxidation-resistance improving element. The second layer (Z) is directly connected, at least partially, to the passivation film.
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