Circuit systems and methods using prime number interleave optimization for byte lane to time slice conversion
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United States of America Patent
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May 20, 2014
Grant Date -
Apr 3, 2014
app pub date -
Sep 28, 2012
filing date -
Sep 28, 2012
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Abstract
Circuit systems and methods use prime number interleave optimization for byte lane to time slice conversion of incoming data streams. Generally, the systems and methods buffer data for at least a number of samples equal to the number of byte lanes. Then the samples are transferred to a bank of buffers whose width is the smallest prime number greater than or equal to the number of byte lanes, N. Thus, the systems and methods utilize P minus N phantom lanes. As data is transferred, the data is circularly interleaved (position*N modulo P) so that all data which will be needed at the same time wind up in different readable devices, i.e. the buffers. By appropriate addressing, the data in the different readable devices may then be read in the form of time slices. The process can be reversed for time slice to byte lane conversion.
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