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Abstract

A system, method, and computer program product for retaining coherent cache contents during deep power-down operations, and reducing the low-power state entry and exit overhead to improve processor energy efficiency and performance. The embodiments flush or clean the Modified-state lines from the cache before entering a deep low-power state, and then implement a deferred snoop strategy while in the powered-down state. Upon existing the powered-down state, the embodiments process the deferred snoops. A small additional cache and a snoop filter (or other cache-tracking structure) may be used along with additional logic to retain cache contents coherently through deep power-down operations, which may span multiple low-power states.

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First Claim