Volatile memory access via shared bitlines
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United States of America Patent
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May 26, 2015
Grant Date -
Apr 10, 2014
app pub date -
Dec 10, 2013
filing date -
Dec 6, 2011
priority date (Note) -
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Abstract
A memory includes an array of memory cells that form rows and columns. The rows of the array include memory cell pairs. The memory cells may include two cross-coupled inverters and two pass-devices that couple to alternate sides of the cross-coupled inverters. The two memory cells of a memory cell pair share a common intra-pair bitline. Adjacent memory cell pairs share a common inter-pair bitline. To perform a data read operation on a particular memory cell in a memory cell pair in the rows and columns of the array, wordline drive circuitry transmits wordline activate signals to select both the row for the data read operation and a particular one of the pair of memory cells for the data read operation.
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