Semiconductor device processing with reduced wiring puddle formation
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United States of America Patent
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Apr 28, 2015
Grant Date -
Apr 10, 2014
app pub date -
Oct 10, 2012
filing date -
Oct 10, 2012
priority date (Note) -
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Abstract
A method of forming an interconnect structure for a semiconductor device includes forming a lower antireflective coating layer over a dielectric layer; forming an organic planarizing layer on the lower antireflective coating layer; transferring a wiring pattern through the organic planarizing layer; transferring the wiring pattern through the lower antireflective coating layer; and transferring the wiring pattern through the dielectric layer, wherein unpatterned portions of the lower antireflective coating layer serve as an etch stop layer so as to prevent any bubble defects present in the organic planarizing layer from being transferred to the dielectric layer.
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