Programmable logic device
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United States of America Patent
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Jul 26, 2016
Grant Date -
Apr 17, 2014
app pub date -
Oct 11, 2013
filing date -
Oct 17, 2012
priority date (Note) -
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status (Latency Note)
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Abstract
To obtain a PLD that achieves high-speed configuration capable of dynamic configuration, consumes less power, and has a short startup time and a PLD that has a smaller number of transistors or a smaller circuit area than a PLD using an SRAM as a configuration memory, a plurality of logic elements arranged in an array and a switch for selecting electrical connection between the logic elements are provided. The switch includes a first transistor including a multilayer film including an oxide layer and an oxide semiconductor layer, a node that becomes floating when the first transistor is turned off, and a second transistor in which electrical continuity between a source and a drain is determined based on configuration data held at the node.
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