Duty cycle protection circuit

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United States of America Patent

PATENT NO 9197197
APP PUB NO 20140103972A1
SERIAL NO

14050203

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Importance

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Abstract

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A duty cycle protection circuit including a first synchronous device adapted to receive a first clock signal on an input line and to generate a first clock transition of a second clock signal in response to a first clock transition of the first clock signal; and reset circuitry coupled to the input line and adapted to generate a second clock transition of the second clock signal by resetting the first synchronous device a time delay after the first clock transition of the first clock signal.

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Patent Owner(s)

  • MENTOR GRAPHICS CORPORATION;STMICROELECTRONICS S.A.

International Classification(s)

Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Asquini, Anna Corenc, FR 1 2
Vallet, Vincent Mennecy, FR 14 319

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