Leakage-current abatement circuitry for memory arrays
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United States of America Patent
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Nov 17, 2015
Grant Date -
Apr 17, 2014
app pub date -
Feb 26, 2013
filing date -
Oct 16, 2012
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Abstract
In one memory array embodiment, in order to compensate for bit-line leakage currents by OFF-state bit-cell access devices, a leakage-current reference circuit tracks access-device leakage current over different process, voltage, and temperature (PVT) conditions to generate a leakage-current reference voltage that drives a different leakage-current abatement device connected to each different bit-line to inject currents into the bit-lines to compensate for the corresponding leakage currents. In one implementation, the leakage-current reference circuit has a device that mimics the leakage of each access device configured in a current mirror that drives the resulting leakage-current reference voltage to the different leakage-current abatement devices.
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