System and method for operating system aware low latency interrupt handling

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United States of America Patent

PATENT NO 9772960
SERIAL NO

13649762

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Abstract

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The exemplary embodiments described herein relate to systems and methods for operating system aware low latency handling. One embodiment relates to a non-transitory computer readable storage medium including a set of instructions executable by a processor, the set of instructions, when executed, resulting in a performance of receiving a fast interrupt request asserted by a hardware device while the processor is executing within a kernel critical section, executing a fast interrupt handler at a first priority level, raising a second priority level interrupt by the fast interrupt handler based on the fast interrupt request, wherein the second priority level interrupt invokes a kernel service and processing the second priority level interrupt once the processor has executed the kernel critical section.

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Patent Owner(s)

  • WIND RIVER SYSTEMS, INC.

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Burton, Felix Foster City, US 16 255
Gaiarsa, Andrew Carp, CA 9 119
Koning, Maarten Bloomfield, CA 26 946

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