Memory system for error detection and correction coverage
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United States of America Patent
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Dec 22, 2015
Grant Date -
Apr 17, 2014
app pub date -
May 14, 2012
filing date -
Jun 6, 2011
priority date (Note) -
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Abstract
A memory system supporting error detection and correction (EDC) coverage. The system includes a memory controller and a memory buffer. The memory buffer includes an interface to a first group of memory devices and an interface to a second group of memory devices. The memory buffer accesses data from the first group of memory devices and accesses first error information corresponding to the data from the second group of devices. The memory buffer also accesses additional data from the second group of memory devices and accesses second error information corresponding to the additional data from a device in the first group of memory devices. EDC coverage may also be configured by the memory controller so that some data accesses have EDC coverage and other data accesses do not have EDC coverage.
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