PACKAGING PROCESS
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United States of America Patent
Stats
-
N/A
Issued Date -
Apr 24, 2014
app pub date -
Dec 7, 2012
filing date -
Oct 18, 2012
priority date (Note) -
Abandoned
status (Latency Note)
Importance
Abstract
A packaging process is provided. A package mother board having an upper surface, a lower surface, a device disposing area and a peripheral area surrounding the device disposing area is provided. Multiple semiconductor devices are disposed on the upper surface. The semiconductor devices are located in the device disposing area. A carrier having a center area and an edge area surrounding the center area is provided. An adhesive layer is formed between the peripheral area and the edge area. The center area of the carrier is disposed corresponding to the device disposing area of the package mother board. The edge area of the carrier is disposed corresponding to the peripheral area of the package mother board. The adhesive layer is in a state of semi-curing, and the package mother board is bonded to the carrier via the adhesive layer. A baking process is performed to completely cure the adhesive layer.
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