Highly secure and extensive scan testing of integrated circuits
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United States of America Patent
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Mar 10, 2015
Grant Date -
May 15, 2014
app pub date -
Apr 8, 2013
filing date -
Oct 16, 2012
priority date (Note) -
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Abstract
In one embodiment, an integrated circuit chip has an input/output (I/O) interface and programmable fabric. The I/O interface restricts access to scan testing of the chip by requiring (1) a specific scan-testing instruction, (2) a specific manufacturing key, and (3) a specific fabric pattern value from a specific set of registers in the programmed fabric. In addition or alternatively, the I/O interface has circuitry that enables scan testing of most of the logic of the I/O interface itself, including the logic being driven by the JTAG TAP state register.
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