Memory Device Interconnects and Method of Manufacture
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United States of America Patent
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app pub date -
Dec 10, 2013
filing date -
May 6, 2008
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Abandoned
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Abstract
An integrated circuit memory device, in one embodiment, includes a substrate having a plurality of bit lines. A first and second inter-level dielectric layer are successively disposed on the substrate. Each of a plurality of source lines extend through the first inter-level dielectric layer. Each of a plurality of source line vias extend through the second inter-level dielectric layer to each respective one of the plurality of source lines. Each of the plurality of staggered bit line contacts extend through the first and second inter-level dielectric layes to respective bit lines.
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