Fast memory read-out
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United States of America Patent
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Jun 23, 2015
Grant Date -
May 29, 2014
app pub date -
Nov 26, 2012
filing date -
Nov 26, 2012
priority date (Note) -
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Abstract
Embodiments include systems and methods for faster memory read-out using a combined read-select circuit. A novel read-select circuit is described, which, when enabled for reading, concurrently reads its respective input line and selects its value for read-out by the circuit. This can reduce delays and unnecessary toggling resulting from separate read and select circuits. Some implementations also include a multi-global-line architecture that can reduce the number of read stages in the memory read-out circuitry, thereby further reducing read-out delays. Accordingly, embodiments can be faster and more efficient than many traditional implementations without relying on an increase in power consumption or clock speed.
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