STRESS EFFECT MODEL OPTIMIZATION IN INTEGRATED CIRCUIT SPICE MODEL
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United States of America Patent
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Issued Date -
May 29, 2014
app pub date -
Jul 16, 2013
filing date -
Nov 23, 2012
priority date (Note) -
Abandoned
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Abstract
A method and apparatus for stress effect model optimization in IC SPICE model and an IC fabrication method are disclosed. The method for optimizing a stress effect model in an integrated circuit model including obtaining values of at least one layout parameter for a plurality of layout areas in an integrated circuit layout; obtaining values of at least one processing parameter for a plurality of wafer areas corresponding to the layout areas; based on the obtained values of the layout parameter and the obtained values of the process parameter, establishing a function representative of dependency of the process parameter on the layout parameter; and applying the function as a process model parameter to the stress effect model.
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