Charge Trapping Device with Improved Select Gate to Memory Gate Isoloation
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United States of America Patent
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Issued Date -
Jun 19, 2014
app pub date -
Dec 14, 2012
filing date -
Dec 14, 2012
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Abandoned
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Abstract
Embodiments described herein generally relate to charge-trapping memory with improved isolation between a select gate and a memory gate. The isolation is improved because the charge trapping layer is not present in the junction between the select gate and the memory gate. The methods described herein additionally allow insulation to be disposed between the select gate and the memory gate.
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