Method and Apparatus for Isolating and/or Debugging Defects in Integrated Circuit Designs

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United States of America Patent

APP PUB NO 20140173539A1
SERIAL NO

13719559

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Abstract

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Method and apparatus for debugging aspects of integrated circuit (IC) designs employ techniques by which defective intellectual property (IP) in those IC designs can be exercised, and defects identified, without disturbing the IP itself, but at the same time isolating the source of the defect(s) to the responsible IP provider(s). The IP provider then can debug the IP. In one aspect, the techniques give the IP provider(s) specific information about the nature of the defect, facilitating the provider's efforts to debug the IP.

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Patent Owner(s)

Patent OwnerAddress
CADENCE DESIGN SYSTEMS INC2655 SEELY AVENUE SAN JOSE CA 95134

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Lin, Tsair-Chin San Jose, US 10 116
Zhang, David Guoqing San Jose, US 6 0

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