Method and Apparatus for Isolating and/or Debugging Defects in Integrated Circuit Designs
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United States of America Patent
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Issued Date -
Jun 19, 2014
app pub date -
Dec 19, 2012
filing date -
Dec 19, 2012
priority date (Note) -
Abandoned
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Abstract
Method and apparatus for debugging aspects of integrated circuit (IC) designs employ techniques by which defective intellectual property (IP) in those IC designs can be exercised, and defects identified, without disturbing the IP itself, but at the same time isolating the source of the defect(s) to the responsible IP provider(s). The IP provider then can debug the IP. In one aspect, the techniques give the IP provider(s) specific information about the nature of the defect, facilitating the provider's efforts to debug the IP.
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