Method and Apparatus for Verifying Debugging of Integrated Circuit Designs

Number of patents in Portfolio can not be more than 2000

United States of America Patent

APP PUB NO 20140173541A1
SERIAL NO

13719570

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Abstract

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Method and apparatus for verifying debugging aspects of integrated circuit (IC) designs. In one aspect, an IP provider(s) can use the same process that isolated IP defect(s) to demonstrate to the customer (whether an IC designer or an IP consumer such as a smartphone manufacturer) that the debugging was successful, and that errors in operation will not recur. In another aspect, the invention provides a facility that enables the IP provider to demonstrate to an IP consumer that a repaired IP component will work under a sufficiently broad set of circumstances, without that demonstration revealing the provider's proprietary IP to the consumer.

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Patent Owner(s)

Patent OwnerAddress
CADENCE DESIGN SYSTEMS INC2655 SEELY AVENUE SAN JOSE CA 95134

International Classification(s)

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Zhang, David Guoqing San Jose, US 6 0

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