Method and Apparatus for Verifying Debugging of Integrated Circuit Designs
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United States of America Patent
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Issued Date -
Jun 19, 2014
app pub date -
Dec 19, 2012
filing date -
Dec 19, 2012
priority date (Note) -
Abandoned
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Abstract
Method and apparatus for verifying debugging aspects of integrated circuit (IC) designs. In one aspect, an IP provider(s) can use the same process that isolated IP defect(s) to demonstrate to the customer (whether an IC designer or an IP consumer such as a smartphone manufacturer) that the debugging was successful, and that errors in operation will not recur. In another aspect, the invention provides a facility that enables the IP provider to demonstrate to an IP consumer that a repaired IP component will work under a sufficiently broad set of circumstances, without that demonstration revealing the provider's proprietary IP to the consumer.
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