Minimum-spacing circuit design and layout for PICA

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United States of America Patent

PATENT NO 9081049
SERIAL NO

14012668

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Abstract

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PICA test circuits are shown that include a first transistor and a second transistor laid out drain-to-drain, such that a gap between respective drain regions of the first and second transistors has a minimum size allowed by a given fabrication technology.

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Patent Owner(s)

  • INTERNATIONAL BUSINESS MACHINES CORPORATION

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Ainspan, Herschel A New Hempstead, US 31 241
Kim, Seongwon Old Tappan, US 42 278
Stellari, Franco Waldwick, US 73 311
Weger, Alan J Mohegan Lake, US 28 186

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